Delay type flip-flop arrangement using transistor transistor log

Details Delay type flip-flop arrangement using transistor transistor log Delay type flip-flop arrangement using transistor transistor log

1988-08-30

1990-02-13

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307458, 307530, H03K 3284, H03K 19088, H03K 19084

Patent

active

049009494

ABSTRACT:
A flip-flop arrangement receiving a clock signal and an input data and outputting a logical output in accordance with a logical level of the data. The arrangement includes a master flip-flop for transmitting a change in the logical level of the data to a pair of output ends when the clock signal is at a predetermined logical level; a slave flip-flop for latching the data transmitted via the pair of output ends; an output buffer for effecting a buffering of the data latched in the slave flip-flop; and a drive circuit for driving the output buffer. The drive circuit responds to logical levels of data appearing at the pair of output ends of the master flip-flop and, based on the logical levels, drives the output buffer to determine a logical output to be output from the arrangement, thereby reducing a total propagation delay time and realizing a high speed operation without increasing a power dissipation.

REFERENCES:
patent: 4626706 (1986-12-01), Allen et al.

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