Bit blitter with narrow shift register

Details Bit blitter with narrow shift register Bit blitter with narrow shift register

1988-03-04

1990-12-25

Fleming, Michael R.

Boots, shoes, and leggings

364200, 3642595, 3642598, 364238, 3649265, 3649657, 3649476, 364942, 364959, G06F 700, G06F 1520

Patent

active

049808532

ABSTRACT:
The present invention provides a fast bit blitter method and circuit which uses less logic than do prior art bit blitter circuits. A circuit built in accordance with the present invention includes four main components each of which only has as many bit positions as does the data bytes that are being shifted. The four main components are a storage register, a multiplexer bank, a multiplexer selector and a barrel shifter. As data words are serially read out of memory, they are temporarily stored in the register. The multiplexer gates selected bit from the word stored in the register, together with selected bits from the next word that appears on the data bus to the barrel shifter. The barrel shifter does the appropriate shifting. Alternatively, the barrel shifter can be located before the multiplexer in the data path. The amount of time required to shift an image using the present invention is approximately the same amount of time required with the prior art, however, the amount of hardware required is substantially less.

REFERENCES:
patent: 3311896 (1967-03-01), Delmege, Jr. et al.
patent: 3961750 (1976-06-01), Dao
patent: 4317170 (1982-02-01), Wada et al.
patent: 4339795 (1982-07-01), Brereton et al.
patent: 4437166 (1984-03-01), O'Brian
patent: 4653019 (1987-03-01), Hodge et al.
DP8511 BITBLT Processing Unit (BPU), a National Semiconductor Corporation Preliminary Data Specification.

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