Reduced power pipelined static data transfer apparatus

Details Reduced power pipelined static data transfer apparatus Reduced power pipelined static data transfer apparatus

1988-12-15

1990-12-25

Zache, Raulfe B.

Boots, shoes, and leggings

36494834, 36494081, 3649484, 3649488, G06F 1300

Patent

active

049808516

ABSTRACT:
A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

REFERENCES:
patent: 4387294 (1983-06-01), Nakamura et al.
"Introduction to VLSI Systems", Mead and Conway, 1980, Addison-Wesley Publishing Company, pp. 254-263.

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