Boots – shoes – and leggings
Patent
1982-12-10
1985-01-08
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 100
Patent
active
044930534
ABSTRACT:
A synchronous apparatus synchronized to the operation of the slowest device is disclosed, comprising a plurality of devices such as first-in first-out buffer memories (FIFOs) connected to at least one synchronizing mechanism such as a full adder circuit. Each device generates a signal to indicating readiness to operate and a signal indicating completion of operation. Each device receives a signal causing the device to operate and a signal causing the device to stop operating. The synchronizing mechanism generates the operate signal upon sensing the readiness signals of all the devices and continues to generate the operate signal while at least one of the ready signals is sensed. The synchronizing mechanism generates the stop signal upon sensing the completion signal from all of the devices and continues to generate that signal while at least one of the completion signals is sensed.
REFERENCES:
patent: 4153941 (1979-05-01), Caddell
Macrologic Bipolar Microprocessor Data Book, pp. 5-35 through 5-44, (Fairchild Camera and Instrument Corporation, 1976).
9403 First-In First-Out (FIFO) Buffer Memory Device Specification, pp. 7-173 through 7-186, Fairchild TTL Macrologic.
Type '283 4-Bit Binary Full Adders with Fast Carry, Device Specification, pp. 7-415 through 7-419.
AT&T Bell Laboratories
Volejnicek D.
Zache Raulfe B.
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