Dual triggered edge-sensitive asynchrounous flip-flop

Details Dual triggered edge-sensitive asynchrounous flip-flop Dual triggered edge-sensitive asynchrounous flip-flop

1989-05-23

1990-12-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307518, 307445, 307443, H03K 037

Patent

active

049805770

ABSTRACT:
An architecture for bistable circuits with minimized sensitivity to metastability events and with improved operation in signal timing, arbitration, and protocol applications. Conventional edge-triggered flip-flops require input signals to remain present during certain set-up and/or hold time intervals on an input line "data path" for sampling at an instant determined by a separate synchronization input signal. In contrast, the present invention uses two edge-sensitive input lines which are triggered essentially independently without either being synchronized by or depending upon the other. The flip-flops also have twin, independently operable, level sensitive and selected priority PRESET and CLEAR input lines. The active edge or level polarity is programmable for each input line. Alternate embodiments for complementary classes of asynchronous timing perform specific bistable functions, such as set-reset, or toggle.

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