Priority resolver having dynamically adjustable priority levels

Details Priority resolver having dynamically adjustable priority levels Priority resolver having dynamically adjustable priority levels

1982-12-14

1985-01-08

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 946

Patent

active

044930364

ABSTRACT:
A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay. Logic is provided that allows the predetermined priority levels to be adjusted dynamically as a function of system conditions.

REFERENCES:
patent: 3919692 (1975-11-01), Kronies et al.
patent: 3921145 (1975-11-01), Emm et al.

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