Dual port cache with interleaved read accesses during alternate

Details Dual port cache with interleaved read accesses during alternate Dual port cache with interleaved read accesses during alternate

1982-12-06

1985-01-08

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 900, G06F 1300

Patent

active

044930330

ABSTRACT:
A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

REFERENCES:
patent: 4169284 (1979-09-01), Hogan et al.
patent: 4317168 (1982-02-01), Messina et al.
patent: 4345309 (1982-08-01), Arulpragasm et al.
patent: 4371929 (1983-02-01), Braun et al.
patent: 4426681 (1984-01-01), Bacot

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