Boots – shoes – and leggings
Patent
1991-02-27
1993-04-13
Shaw, Gareth D.
Boots, shoes, and leggings
364DIG1, 3642301, 3642318, 3642323, 3642804, G06F 945, G06F 938
Patent
active
052029930
ABSTRACT:
A method and apparatus for cost based heuristic instruction scheduling for a pipelined processor is disclosed which has particular application to compile time instruction scheduling after code generation. The method and apparatus schedules instructions of an instruction block one at a time, based on the lowest total cost among all the current eligible free instructions. The total cost of each of the current eligible free instructions is computed based on the weighted sum of a plurality of cost heuristics. The cost heuristics used in the preferred embodiment comprise a resource dependency cost, a data dependency cost, a dependency wait cost, a dependent cycle cost, a floating point ratio cost, a store ratio cost and a floating point queue cost. Additionally, in the preferred embodiment, a number of the cost heuristics are modeled by a processor model. As a result, improved overall effectiveness in speeding up the execution time of an instruction block is achieved.
REFERENCES:
Gibbons, P. B. and Muchnick, S. S., "Efficient Instruction Scheduling for a Pipelined Architecture", Proc. of the SIG PLAN '86 Symp. on Computer Construction, 1986.
Tarsy Gregory
Woodard Michael J.
Katbab A.
Shaw Gareth D.
Sun Microsystems Inc.
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