Information processor for performing processing without register

Details Information processor for performing processing without register Information processor for performing processing without register

1997-09-03

2000-08-08

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712 41, 712210, 712215, 712216, 712217, 712218, G06F 900

Patent

active

061015962

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to an information or data processor that processes and executes instructions on a pipeline basis. More particularly, the invention relates to an information or data processor (simply called an information processor hereunder) for processing information or data in an environment where short and long latency processes are mixed.
The biggest constraint on instruction control by an information processor that processes instructions on a pipeline basis as programmed is that the processor must execute the instructions in a sequence consistent with the software-designated instruction execution order.
Typical pipeline-processing information processors perform what may be termed basic pipeline processing having each instruction completed in about three to five cycles. In this type of processing, instruction execution may be carried out one cycle at a time (called short latency processing hereunder).
The instructions are not limited to short latency processing alone; some instructions are complicated and take some time to execute (called long latency processing hereunder). The complicated or time-consuming instructions illustratively represent divisions and main memory access operations. This makes it difficult to meet the above consistency requirement at all times.
There have been proposed ways to bypass the above constraint regardless of the duration of pipeline processing being short or long, i.e., irrespective of short or long latency processes being carried out.
The simplest way to satisfy the requirement of instruction execution sequence consistency is that, when an instruction performs a process other than a basic pipeline process, all subsequent instructions are kept from proceeding to execution (the scheme is called the interlock method).
The following series of instructions will be discussed below as an example:
If the instruction (1) turns out to have a long execution cycle (i.e., a long latency process instruction) when executed, then the interlock method causes the instruction (2) and all subsequent instructions to be interlocked.
Alternatively, if the instructions (2) and (3) are independent of the outcome of the instruction (1), the two instructions may be executed ahead of the latter to enhance execution performance. This method involves using a detector that checks during execution of the instruction (1) to see if the subsequent instructions are dependent on the result of the execution of the instruction (1). If the subsequent instructions are found to be independent of the ongoing instruction, these instructions are executed without delay. If the subsequent instructions are found to be dependent on the outcome of the ongoing instruction, processing is allowed to proceed up to the currently executed instruction, the dependent instructions are interlocked therewith. These methods are implemented so as to process instructions in a consistent sequence.
Of particular importance regarding instruction dependency is a possible conflict that may occur between general registers. There are two representative ways to detect register conflict. One way is to compare the number of the register holding the instruction for each pipeline with the numbers of the registers accommodating instructions to be subjected to pipeline processing. The other way to detect possible register conflict is the use of what is known as a scoreboard.
A scoreboard comprises a bit indicating the number of the register accommodating the instruction currently treated in pipeline processing; setting means for setting the bit to 1; and resetting means for resetting the bit to 0. A register conflict is detected by the scoreboard checking to see whether the bit corresponding to the register for an instruction to be put to pipeline processing is 1 or 0.
The method for interlocking instructions upon comparison of register numbers, i.e., a first conventional method, is discussed illustratively in Japanese Patent Laid-Open No. Hei 5-298091. The publication discloses an information processor

REFERENCES:
patent: 4875160 (1989-10-01), Brown, III
patent: 5142631 (1992-08-01), Murray et al.
patent: 5167026 (1992-11-01), Murray et a.
patent: 5276822 (1994-01-01), Maekawa et al.
patent: 5471591 (1995-11-01), Edmondson et al.
patent: 5488730 (1996-01-01), Brown, III et al.
patent: 5632023 (1997-05-01), White et al.
patent: 5761475 (1998-06-01), Yung et al.

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