High-fanout clock driver for low level gates

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307445, 307465, 307456, H03K 1920, H03K 1712, H03K 19088

Patent

active

046251278

ABSTRACT:
A clock driver circuit for low level gates having high fanout capabilities includes a first circuit portion, a second circuit portion, an output transistor and a load resistor. The first circuit portion is formed of a first NAND logic gate and a first inverter gate. The input node of the first inverter circuit gate is coupled to the output node of the first NAND gate. The input node of the first NAND gate is connected to an input circuit terminal. The second circuit portion is formed of a second NAND logic gate, a third NAND logic gate and a second inverter gate. The input nodes of the second and third NAND gates are coupled together and to the input circuit terminal. The output node of the second and third NAND gates are coupled together and to the input node of the second inverter gate. The output node of the second inverter gate is connected to an output circuit terminal. The output transistor has its base coupled to the output node of the first inverter gate, its collector coupled to a voltage supply potential and its emitter coupled to the output circuit terminal. The load resistor has its one end connected to the base of the output transistor and its other end connected to the voltage supply potential.

REFERENCES:
patent: 3145309 (1964-08-01), Bothwell et al.
patent: 3287719 (1966-11-01), Thornberg et al.
patent: 3538443 (1970-11-01), Tague
patent: 3579119 (1971-05-01), Yau
patent: 4337465 (1982-06-01), Spracklen et al.
patent: 4477738 (1984-10-01), Kouba
patent: 4564773 (1986-01-01), Tanizawa et al.

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