Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Patent
1991-05-21
1993-04-13
Larkins, William D.
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
257141, 257144, 257373, H01L 2974, H01L 2978
Patent
active
052025730
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device and, more particularly, to an integrated circuit device in which a plurality of thyristors having MOS gates are formed on one semiconductor substrate.
BACKGROUND ART
A conventional semiconductor circuit device in which a plurality of MOS thyristors are formed on a semiconductor substrate is arranged as shown in FIG. 15, and the circuit device has a p-type silicon substrate 51 containing boron (B) having a concentration of about 10.sup.14 /cm.sup.3. After a silicon oxide layer is coated on the surface of the silicon substrate 51 by a conventional thermal oxidation process, openings are formed in the oxide silicon layer by a photoetching process using a mask, and boron is doped in the silicon substrate 51 through the openings. Thereafter, the oxide silicon layer is removed, and an n.sup.- -type epitaxial growing layer 52 is formed. With this epitaxial growing process, the boron doped in the substrate 51 is diffused, and a p.sup.+ -type buried layer 53 is formed. A p-type impurity region 54 connected to the p.sup.+ -type buried layer 53 is formed in the surface region of the layer 52, an the n.sup.- -type exitaxial region of the layer 52, and the n.sup.- -type epitaxial growing layer 52 is divided into two regions 521 and 522 by the p.sup.+ -type buried layer 53 and the p-type impurity layer 54 which are connected to each other.
In the surface region of the p-type impurity layer 54, a high-concentration p.sup.+ -type impurity region 55 is formed, and n.sup.+ -type regions 56 and 57 are formed on both the sides of the p.sup.+ -type region 55. A cathode C is formed to be electrically connected to the n.sup.+ -, p.sup.+ -, and n.sup.+ -type impurity regions 56, 55, and 57 which are continuously connected.
Anode regions 59 and 60 are formed in the n.sup.31 -type epitaxial layer 52 so as to be divided by the buried layer 53 and the impurity layer 54. Anodes A1 and A2 constituted by the p-type impurity regions 61 and 62 and the high-concentration p.sup.+ -type impurity regions 63 and 64 are formed in the anode regions 59 and 60, respectively.
P-n junction portions constituted by the n.sup.- -type epitaxial layer 52, the p-type impurity region 54, and the n.sup.+ -type impurity regions 56 and 57 are exposed on the surface of the n.sup.- -type epitaxial layer 52. Gates G1 and G2 are formed by polysilicon 67 and polysilicon 68 through gate insulating films in the p-n junction portions, respectively.
That is, the n.sup.+ -type impurity regions 56 and 57 in the cathode region are connected to the n.sup.+ -type impurity regions 61 and 62 in the anode regions through the p-type impurity region 54 and the n.sup.- -type epitaxial layer 52, respectively. Thus, p-n-p-n junctions are arranged in a lateral direction, thereby constituting an IGBT.
In an integrated circuit device with the above arrangement, a sufficient voltage is applied to the gate G1 to turn it on, and the gate G2 has the same potential as that of the anode A2 and is then turned off. In this case, holes injected from the anode A1 serving as a drain reach the n.sup.- -type epitaxial region 522 adjacent to the region 521 from the n.sup.- -type epitaxial region 521. At this time, since the n.sup.- -type epitaxial region 522 in an OFF state has a high potential, the holes flow to the region 522.
The present invention has been made in consideration of the above problem, and has as its object to a semiconductor integrated circuit device in which, when a plurality of MOS thyristors are formed near the same surface of a semiconductor substrate, the thyristor elements are independently controlled without any influence on each other.
SUMMARY OF THE INVENTION
In an integrated circuit device according to the present invention, a semiconductor layer of a second conductivity type is stacked on a semiconductor substrate of a first conductivity type, a pair of first impurity regions of the first conductivity type are formed throughout the semiconductor layer from its surface to t
REFERENCES:
patent: 4403395 (1983-09-01), Curran
patent: 4628341 (1986-12-01), Thomas
patent: 4755697 (1988-07-01), Kinzer
Robinson et al., Lateral Insulated Gate Transistors with Improved Latching Characteristics, IEEE Electron Device Letters, vol. EDL-7, No. 2, Feb. 1986.
Kabushiki Kaisha Toshiba
Larkins William D.
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