Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Patent
1997-09-18
2000-08-08
Patel, Ajit
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
370516, 370503, 375371, H04J 306
Patent
active
061011975
ABSTRACT:
A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi--tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.
REFERENCES:
patent: 4077016 (1978-02-01), Sanders et al.
patent: 4096402 (1978-06-01), Schroeder et al.
patent: 4404474 (1983-09-01), Dingwall
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4511846 (1985-04-01), Nagy et al.
patent: 4514647 (1985-04-01), Shoji
patent: 4638187 (1987-01-01), Boler et al.
patent: 4687951 (1987-08-01), McElroy
patent: 4773085 (1988-09-01), Cordell
patent: 4789796 (1988-12-01), Foss
patent: 4893087 (1990-01-01), Davis
patent: 4902986 (1990-02-01), Lesmeister
patent: 4958088 (1990-09-01), Farah-Bakhsh et al.
patent: 4984204 (1991-01-01), Sato et al.
patent: 5020023 (1991-05-01), Smith
patent: 5038115 (1991-08-01), Myers et al.
patent: 5086500 (1992-02-01), Greub
patent: 5087828 (1992-02-01), Sato et al.
patent: 5122690 (1992-06-01), Bianchi
patent: 5128560 (1992-07-01), Chern et al.
patent: 5128563 (1992-07-01), Hush et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5165046 (1992-11-01), Hessen
patent: 5179298 (1993-01-01), Hirano et al.
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5212601 (1993-05-01), Wilson
patent: 5220208 (1993-06-01), Schenck
patent: 5239206 (1993-08-01), Yanai
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5256989 (1993-10-01), Parker et al.
patent: 5257294 (1993-10-01), Pinto et al.
patent: 5268639 (1993-12-01), Gasbarro et al.
patent: 5274276 (1993-12-01), Casper et al.
patent: 5276642 (1994-01-01), Lee
patent: 5278460 (1994-01-01), Casper
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5283631 (1994-02-01), Koerner et al.
patent: 5295164 (1994-03-01), Yamamura
patent: 5311481 (1994-05-01), Casper et al.
patent: 5311483 (1994-05-01), Takasugi
patent: 5321368 (1994-06-01), Hoelzle
patent: 5337285 (1994-08-01), Ware et al.
patent: 5347177 (1994-09-01), Lipp
patent: 5347179 (1994-09-01), Casper et al.
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5361002 (1994-11-01), Casper
patent: 5390308 (1995-02-01), Ware et al.
patent: 5400283 (1995-03-01), Raad
patent: 5408640 (1995-04-01), MacIntyre et al.
patent: 5410263 (1995-04-01), Waizman
patent: 5420544 (1995-05-01), Ishibashi
patent: 5428311 (1995-06-01), McClure
patent: 5430676 (1995-07-01), Ware et al.
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5438545 (1995-08-01), Sim
patent: 5440260 (1995-08-01), Hayashi et al.
patent: 5440514 (1995-08-01), Flannagan et al.
patent: 5446696 (1995-08-01), Ware et al.
patent: 5448193 (1995-09-01), Baumert et al.
patent: 5451898 (1995-09-01), Johnson
patent: 5457407 (1995-10-01), Shu et al.
patent: 5465076 (1995-11-01), Yamauchi et al.
patent: 5473274 (1995-12-01), Reilly et al.
patent: 5473575 (1995-12-01), Farmwald et al.
patent: 5473639 (1995-12-01), Lee et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5488321 (1996-01-01), Johnson
patent: 5489864 (1996-02-01), Ashuri
patent: 5497127 (1996-03-01), Sauer
patent: 5498990 (1996-03-01), Leung et al.
patent: 5506814 (1996-04-01), Hush et al.
patent: 5508638 (1996-04-01), Cowles et al.
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5539345 (1996-07-01), Hawkins
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5552727 (1996-09-01), Nakao
patent: 5568075 (1996-10-01), Curran et al.
patent: 5568077 (1996-10-01), Sato et al.
patent: 5572557 (1996-11-01), Aoki
patent: 5574698 (1996-11-01), Raad
patent: 5576645 (1996-11-01), Farwell
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5578940 (1996-11-01), Dillon et al.
patent: 5578941 (1996-11-01), Sher et al.
patent: 5581197 (1996-12-01), Motley et al.
patent: 5589788 (1996-12-01), Goto
patent: 5590073 (1996-12-01), Arakawa et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5619473 (1997-04-01), Hotta
patent: 5621340 (1997-04-01), Lee et al.
patent: 5621690 (1997-04-01), Jungroth et al.
patent: 5627780 (1997-05-01), Malhi
patent: 5627791 (1997-05-01), Wright et al.
patent: 5631872 (1997-05-01), Naritake et al.
patent: 5636163 (1997-06-01), Furutani et al.
patent: 5636173 (1997-06-01), Schaefer
patent: 5636174 (1997-06-01), Rao
patent: 5638335 (1997-06-01), Akiyama et al.
patent: 5657481 (1997-08-01), Farmwald et al.
patent: 5668763 (1997-09-01), Fujioka et al.
patent: 5692165 (1997-11-01), Jeddeloh et al.
patent: 5694065 (1997-12-01), Hamasaki et al.
patent: 5712580 (1998-01-01), Baumgartner et al.
patent: 5751665 (1998-05-01), Tanoi
Anonymous, "Programmable Pulse Generator", IBM Technical Disclosure Bulletin, vol. 17, No. 12, May 1975, pp. 3553-3554.
Anonymous, "Pulse Combining Network", IBM Technical Disclosure Bulletin, vol. 32, No. 12, May 1990, pp. 149-151.
Hamamoto, T., "400-MHz Random Column Operating SDRAM Techniques with Self-Skew Compensation," IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 770-778.
Taguchi, M. et al., "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture", IEEE Journal of Solid-State Circuits, vol. 26, Nov. 1991, pp. 1493-1497.
Alvarez, J. et al. "A Wide-Bandwidth Low Voltage PLL for PowerPC .TM.Microprocessors" IEEE IEICE Trans. Electron., vol. E-78. No. 6, Jun. 1995, pp. 631-639.
Aviram, A. et al., "Obtaining High Speed Printing On Thermal Sensitive Special Paper With A Resistive Ribbon Print Head", IBM Technical Disclosure Bulletin, vol. 27, No. 5, Oct. 1984, pp. 3059-3060.
Chapman, J. et al., "A Low-Cost High-Performance CMOS Timing Vernier for ATE", IEEE International Test Conference, Paper 21.2, 1995, pp. 459-468.
Cho, J. "Digitally-Controlled PLL with Pulse Width Detection Mechanism for Error Correction", ISSCC 1997, Paper No. SA 20.3, pp. 334-335.
Christiansen, J., "An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops", IEEE Journal of Solid-State Circuits, vol. 31, No. 7, July 1996, pp. 952-957.
Combes, M. et al., "A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells", IEEE Journal of Solid-State Circuits, vol. 31, No. 7, July 1996, pp. 958-965.
"Draft Standard for a High-Speed Memory Interface (SyncLink)", Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.
Goto, J. et al., "A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors", IEICE Trans. Electron., vol. E77-C, No. 12, Dec. 1994, pp. 1951-1956.
Ishibashi, A. et al., "High-Speed Clock Distribution Architecture Employing PLL for 0.6.mu. CMOS Sog", IEEE Custon Integrated Circuits Conference, 1992, pp. 27.6.1-27.6.4
Kim, B. et al., "A 30MHz High-Speed Analog/Digital PLL in 2.mu. CMOS", ISSCC, February 1990.
Kikuchi, S. et al., "A Gate-Array-Base
Keeth Brent
Manning Troy A.
Micro)n Technology, Inc.
Patel Ajit
Pizarro Ricardo M.
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