Method of operating a synchronous memory device

Details Method of operating a synchronous memory device Method of operating a synchronous memory device

1998-12-17

2000-08-08

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 700

Patent

active

061011525

ABSTRACT:
A synchronous memory device having a plurality of memory cells and a method of operation thereof. The memory device comprising: receiver circuitry to receive a first external clock signal; and output driver circuitry, to output data after a preprogrammed number of clock cycles of the first external clock signal transpire. The data is output synchronously with respect to the first external clock signal. The method of operation comprises: receiving a request for a read operation; sensing data in a portion of the plurality of sense amplifiers in response to the request for a read operation; and outputting the data after a preprogrammed delay time transpires. The method may further include receiving an external clock signal wherein the preprogrammed time delay is representative of a fixed number of clock cycles of the external clock signal. The data is output synchronously with respect to the first external clock signal.

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