Semiconductor memory having test circuit and test method thereof

Details Semiconductor memory having test circuit and test method thereof Semiconductor memory having test circuit and test method thereof

1992-02-14

1995-03-21

Baker, Stephen M.

Excavating

365200, 365201, 371 103, 371 211, G11C 2900

Patent

active

054003423

ABSTRACT:
A semiconductor memory includes a plurality of memory cells which are arranged in a matrix and respectively store data, a plurality of bit lines and a plurality of word lines, connected to the plurality of memory cells, for performing read/write access of data to the memory cells, and a test circuit. In the test circuit, an external terminal sends test data and expected value data written in the memory cells. A simultaneous write circuit simultaneously writes the test data from the external terminal in the plurality of memory cells connected to a selected word line. A simultaneous comparison circuit simultaneously compares the test data written in the plurality of memory cells connected to the selected word line with the expected value data supplied from the external terminal in correspondence with the selected word line.

REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4601019 (1986-07-01), Shah et al.
patent: 4654827 (1987-03-01), Childers
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4661930 (1987-04-01), Tran
patent: 4667330 (1987-05-01), Kumagai
patent: 4670878 (1987-06-01), Childers
McAdams, H. et al., "A 1-Mbit CMOS Dynamic RAM With Design-For-Test Functions", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 635-641.
Le, K. et al., "A Novel Approach for Testing Memories Using a Built-In Self Testing Technique", 1986 International Test Conf., pp. 830-839.
Lo, T. et al., "An Integrated Test Concept for Switched-Capacitor Dynamic MOS RAM's", IEEE Jour. of Solid-State Circuits, vol. SC-12, No. 6, Dec. 1977, pp. 693-703.
Mazumder, P. et al., "Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories", 24 ACM/IEEE Design Automation Conf., Jul. 1987, pp. 688-694.
Sridhar, T., "A New Parallel Test Approach for Large Memories", 1985 International Test Conf., pp. 462-470.
"A 90ns 1Mb DRAM with Multi-Bit Test Mode" by M. Kumanoya et al., 1985 IEEE International Solid-State Circuits Conference, pp. 240, 241.
"Redundancy Test for 1 Mbit DRAM using Multi-Bit-Test Mode" by Y. Nishimura et al., 1986 IEEE International Test Conference, pp. 826-829.

Affiliated with

Also associated with

Rating

Semiconductor memory having test circuit and test method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory having test circuit and test method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory having test circuit and test method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1155265