Fishing – trapping – and vermin destroying
Patent
1991-11-08
1993-04-13
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 44, 437150, 437913, 148DIG126, H01L 21265
Patent
active
052022765
ABSTRACT:
This is a DMOS transistor and a method of forming a DMOS transistor structure. The method comprises: forming a polycrystalline silicon central gate region; forming a drain region in the substrate self-aligned to the central gate region; forming polycrystalline silicon gate sidewalls adjacent to the gate region; and forming a source region in the substrate self-aligned to the edges of the sidewalls. It can provide a channel region which is significantly longer (Ld) than it is in depth (essentially Lj) can be produced between the source region and the drain region, and thus the method provides an optimization of the transistor for lower on-resistance and thus a DMOS device having a MOS channel length longer than its parasitic JFET channel length. Preferably channel regions are formed which are 0.25-0.75 um in depth and the channel regions have an Ld of 1.0-2.5 um.
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Donaldson Richard L.
Hearn Brian E.
Kesterson James C.
Stoltz Richard A.
Texas Instruments Incorporated
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