Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Patent
1997-08-27
2000-08-08
Zimmerman, Mark K.
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
345442, 345505, G06T 1500
Patent
active
06100894&
ABSTRACT:
A high order surface patch rendering system with adaptive tessellation. A patch is rendered by subdividing a patch until the subpatches are sufficiently flat that they can be approximated by a quadrilateral. To subdivide a patch, the patch rendering system uses a patch division unit which accepts the control points of a patch and divides the patch in half by determining the control points of a subpatch. The relationship of the patch to it's subpatches is that of a binary tree, where every patch division produces two subpatches which may themselves be subject to patch division. In one embodiment, the patch division unit is able to traverse the binary subdivision tree in three directions (parent to left-child, left-child to right-sibling, and right-sibling to parent) to minimize memory requirements. In this embodiment the patch division unit comprises a set of curve division units. An X-curve division unit is coupled to a patch buffer to receive current X coordinates for the set of control points for the current patch, and configured to convert the current X coordinates into new X coordinates for the control points of the new patch. A Y-curve division unit is coupled to the patch buffer to receive current Y coordinates for the set of control points for the current patch, and configured to convert the current Y coordinates into new Y coordinates for the control points of the new patch. A Z-curve division unit is coupled to the patch buffer to receive current Z coordinates for the set of control points for the current patch, and configured to convert the current Z coordinates into new Z coordinates for the control points of the new patch. Each of the curve division units is further configured to receive an operation type signal and configured to generate coordinates for (a) a left subpatch if the operation type signal indicates a left child operation, (b) a right subpatch if the operation type signal indicates a right sibling operation, and (c) a parent patch if the operation type signal indicates a parent operation.
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Kivlin B. Noel
LSI Logic Corporation
Zimmerman Mark K.
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