Semiconductor integrated circuit device and semiconductor memory

Details Semiconductor integrated circuit device and semiconductor memory Semiconductor integrated circuit device and semiconductor memory

1992-11-13

1995-03-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 365181, 36518905, 326 45, 326121, 327211, G11C 1134

Patent

active

054002958

ABSTRACT:
In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

REFERENCES:
patent: 4766572 (1988-08-01), Kobayashi
patent: 4879687 (1989-11-01), Okamoto et al.
patent: 5040143 (1991-08-01), Matsumura et al.
patent: 5107465 (1992-04-01), Fung et al.
patent: 5280201 (1994-01-01), Fujimori et al.

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