MOS Decoder selection circuit having a barrier transistor whose

Details MOS Decoder selection circuit having a barrier transistor whose MOS Decoder selection circuit having a barrier transistor whose

1981-10-22

1984-12-25

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307443, H03K 19003, H03K 19096, H03K 1730, H03K 17687

Patent

active

044906285

ABSTRACT:
Disclosed is a semiconductor integrated circuit device, which comprises at least one selection circuit including a first node, a first MOS transistor for periodically pre-charging the first node, second MOS transistors for determining the potential state of the first node in response to a state designating signal, a third MOS transistor connected to the first node and functioning as a barrier, a second node connected through the barrier MOS transistor to the first node, a fourth MOS transistor for providing a signal at a level corresponding to the potential state of the second node, and a control circuit for holding the gate potential of the barrier MOS transistor at a low level for a period from the instant when the potential state of the first node is determined till the subsequent pre-charge cycle.

REFERENCES:
patent: 3644904 (1972-02-01), Baker
patent: 3795898 (1974-03-01), Mehta et al.
patent: 4081699 (1978-03-01), Hirt et al.
patent: 4099162 (1978-07-01), Basse
patent: 4145622 (1979-03-01), Hofmann et al.
patent: 4267464 (1981-05-01), Takemae
Dockerty et al., "Enhancement/Depletion Decoder Circuit", IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976.
Huffman et al., "Memory Address Decode Circuit", IBM Technical Disclosure Bulletin, vol. 19, No. 1, Jun. 1976.
Itoh et al., 1980 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 228-229, (2/15/1980).

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