Fishing – trapping – and vermin destroying
Patent
1988-11-01
1992-01-21
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 6, 437203, 357 234, H01L 21266, H01L 21467
Patent
active
050827952
ABSTRACT:
A self aligned method of fabricating a vertical channel insulated gate semiconductor device comprises providing a first layer of one type conductivity atop a partially processed wafer. A first protective layer is disposed over the first layer and a window is opened therethrough. A first region can be established through the first window and in the first layer. A trench is established through the first window, and extending entirely through the first region and first layer, into the partially processed wafer. An insulated gate is established in the trench to control the drift region electric field under reverse bias operation.
REFERENCES:
patent: 3413527 (1968-11-01), Davies
patent: 3855608 (1974-12-01), George et al.
patent: 3953879 (1976-04-01), O'Connor-D'Arlach et al.
patent: 4252579 (1981-02-01), Ho et al.
patent: 4272302 (1981-06-01), Jhabvala
patent: 4295924 (1981-10-01), Garnache et al.
patent: 4502072 (1985-02-01), Herberg
patent: 4502914 (1985-03-01), Trumpp et al.
patent: 4516315 (1985-05-01), Przybysz et al.
patent: 4589193 (1986-05-01), Goth et al.
patent: 4612465 (1986-09-01), Schutten et al.
patent: 4630237 (1986-12-01), Miura et al.
patent: 4639288 (1987-01-01), Price et al.
patent: 4679300 (1987-07-01), Chan et al.
patent: 4683643 (1987-08-01), Nakajima et al.
patent: 4689871 (1987-09-01), Malhi
patent: 4693781 (1987-09-01), Leung et al.
patent: 4754310 (1988-06-01), Coe
patent: 4767722 (1988-08-01), Blanchard
patent: 4772926 (1988-09-01), Nishizawa et al.
Cardon et al., Dynamic Semiconductor RAM Structures, Pergamon Press (Oxford, England 1984), pp. 310-311.
Hu, Chenming, "A Parametric Study of Power MOSFETS", 10th Power Electronics Specialists Conference, Record held Jan. 18-22, 1979, pp. 385-395.
Chaudhuri Olik
Davis Jr. James C.
General Electric Company
Ochis Robert
Ojan Ourmazd
LandOfFree
Method of fabricating a field effect semiconductor device having does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a field effect semiconductor device having, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a field effect semiconductor device having will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-115361