Method of fabricating MOS transistors using selective polysilico

Details Method of fabricating MOS transistors using selective polysilico Method of fabricating MOS transistors using selective polysilico

1990-08-17

1992-01-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437 44, 437 89, 437191, 437233, 148DIG122, H01L 2128, H01L 21336

Patent

active

050827944

ABSTRACT:
In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

REFERENCES:
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Huang et al., "Eliminating Spacer-Induced Degradations in LDD Transistors", 3rd. Int'l. Symposium on VLSI Technology Systems and Applications, May 1987.
Borland et al., "Selective Silicon Deposition for the Megabit Age", Solid State Technology, Jan. 1990, pp. 73-78.
Pfiester et al., "A Self-Aligned LDD/Channel Implanted ITLDD Process with Selectively-Deposited Poly Gates for CMOS VLSI", IEDM 1989, pp. 769-772.

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