Method of manufacturing a device in a silicon wafer

Details Method of manufacturing a device in a silicon wafer Method of manufacturing a device in a silicon wafer

1979-09-06

1981-08-25

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 148187, 357 23, 357 51, 357 91, H01L 21285

Patent

active

042851173

ABSTRACT:
Portions of a doped silicon body 22 are covered with an oxide dielectric 26 leaving the active areas 25 on the silicon body exposed. A polysilicon layer 28 having a predetermined resistance characteristic is formed over the entire wafer surface followed by a layer of silicon nitride 30. Selected portions of the silicon nitride layer 30 are removed with the nitride remaining over the source/drain regions 36 of the active area and the locations of first level conductor runs 32. The exposed polysilicon 28 is converted to an oxide and the silicon nitride 30, covering the source/drain regions 36 and the first level conductor runs, is removed. The exposed polysilicon is doped forming source/drain diffusions 46 and first level conductors 32. An oxide dielectric 52 is formed over the wafer 20 and removed from the gate areas 56 followed by the formation of a thin gate dielectric 54. Finally the oxide 52 is removed at the interconnect work sites and second level conductors 58, 60 are formed. If desired, resistors are formed by allowing the nitride masking layer 30 to remain over selected portions of the polysilicon during the doping of the source/drain areas and first level conductors.

REFERENCES:
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patent: 4016587 (1977-04-01), DeLaMoneda
patent: 4041518 (1977-08-01), Shimizu et al.
patent: 4110776 (1978-08-01), Rao et al.
patent: 4177096 (1979-12-01), Okumura et al.
patent: 4178674 (1979-12-01), Liu et al.
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patent: 4214917 (1980-07-01), Clark et al.
patent: 4219925 (1980-09-01), Heeren
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Nishimatsu et al., Japanese J. of Applied Physics, vol. 16, (1977), Suppl. 16-1, pp. 179-183.
Middelhoek et al., IEEE Transactions on Electron Devices, May 1976, pp. 523-525.

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