Digital PLL circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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Details

327237, 327553, H03K 513, H03L 718, H03L 7087, H03L 7089

Patent

active

053999851

ABSTRACT:
The invention provides a digital PLL circuit wherein the integration time constant of a random walk filter can be varied adaptively in response to a frequency error. A master clock signal having a frequency equal to N (integral number) times that of an input clock signal is normally divided by N by a divider, and the division output of the divider and the input clock signal are compared in phase with each other by a phase comparator. The dividing ratio of the divider is temporarily varied in accordance with a result of the comparison so as to make the phases of the division output and the input clock signal coincide with each other to establish synchronism between them. A variable step number random walk filter is interposed between the phase comparator and the divider and has a selectively settable integration time constant, and an integration time constant setting circuit varies the step number of the random walk filter in accordance with information of a last phase controlling direction or directions and information of a phase controlling direction at present to vary the integration time constant of the random walk filter.

REFERENCES:
patent: 4577163 (1986-03-01), Culp
patent: 4791386 (1988-12-01), Shiga
patent: 5015970 (1991-05-01), Williams et al.
patent: 5077529 (1991-12-01), Ghoshal et al.

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