Multi-chip semiconductor arrangements using flip chip dies

Details Multi-chip semiconductor arrangements using flip chip dies Multi-chip semiconductor arrangements using flip chip dies

1992-11-12

1995-03-21

Sikes, William L.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

257777, 257778, 257723, 257724, H05K 114, H01L 2352, H01L 2354

Patent

active

053998987

ABSTRACT:
Multi-chip, multi-tier semiconductor arrangements based upon single and double-sided flip-chips are described. The double-sided flip chips provide raised bump contact means on both major surfaces of a die and provided connections to internal signals within the die, feed through connections between contacts on opposite sides of the die, and jumpered connections between contacts on the same side of the die. Various multi-chip configurations are described. Certain of these flip-chip configuration dramatically increase the ratio of I/O area (periphery) to footprint area, permitting larger numbers of I/O points within a given assembly footprint than would otherwise be possible in a single die configuration.

REFERENCES:
patent: 4807021 (1989-02-01), Okumura
patent: 4897708 (1990-01-01), Clements
patent: 4982265 (1991-06-01), Watanabe et al.
patent: 5191405 (1993-03-01), Tomita et al.
patent: 5220200 (1993-09-01), Blanton
patent: 5239448 (1993-08-01), Perkins et al.

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