Method and apparatus for performing the square root function usi

Details Method and apparatus for performing the square root function usi Method and apparatus for performing the square root function usi

1989-09-05

1991-10-22

Shaw, Dale M.

Boots, shoes, and leggings

G06F 738

Patent

active

050601822

ABSTRACT:
A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.

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Fandrianto, Jan, "Algorithm for High Speed Shared Radix 4 Division and Radix 4 Square Root", IEEE, 1987, 73-79.
Ramamoorthy et al., "Some Properties of Iterative Square Rooting Methods Using High-Speed Multiplication", IEEE Trans. Comput., (1972) C-21:837-847).
Taylor, George S., "Compatible Hardware for Division and Square Root", IEEE, 1981--127-134.
Parikh, S., "An Architecture for a Rational Arithmetic Unit", Dissertation, Univ. of Bombay, 1978, Univ. of Tex. at Arlington, 1981.

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