Vector processor adopting a memory skewing scheme for preventing

Details Vector processor adopting a memory skewing scheme for preventing Vector processor adopting a memory skewing scheme for preventing

1994-07-15

1996-12-31

Geckil, Mehmet B.

Boots, shoes, and leggings

395454, 395732, 364736, 364DIG1, 36423221, 3642281, G06F 1516

Patent

active

055903533

ABSTRACT:
A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.

REFERENCES:
patent: 5214769 (1993-05-01), Uchida et al.
patent: 5276902 (1994-01-01), Nakatani et al.
patent: 5388247 (1995-02-01), Goodwin et al.
patent: 5392443 (1995-02-01), Sakakibara et al.
patent: 5412788 (1995-05-01), Collins et al.

Affiliated with

Also associated with

Rating

Vector processor adopting a memory skewing scheme for preventing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vector processor adopting a memory skewing scheme for preventing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vector processor adopting a memory skewing scheme for preventing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1150079