Method and apparatus for reducing power consumption in a compute

Details Method and apparatus for reducing power consumption in a compute Method and apparatus for reducing power consumption in a compute

1994-11-29

1996-12-31

Sheikh, Ayaz R.

395280, G06F 1300

Patent

active

055903428

ABSTRACT:
A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMVxD) responsible for performing idle detection for devices. The PMVxD performs idle detection using event timers that provide an indicator as to the activity level. The PMVxD places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.

REFERENCES:
patent: 5167024 (1992-11-01), Smith et al.
patent: 5276888 (1994-01-01), Kardach et al.
patent: 5404321 (1995-04-01), Mattox
patent: 5404546 (1995-04-01), Stewart

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