Method and apparatus for reducing power consumption in a compute

Details Method and apparatus for reducing power consumption in a compute Method and apparatus for reducing power consumption in a compute

1994-09-30

1996-12-31

Harvey, Jack B.

395287, G06F 104

Patent

active

055903410

ABSTRACT:
A computer system that contains devices and peripherals that have power management capabilities incorporated therein that are responsible for placing the computer system in a reduced power consumption state. A controller monitors bus cycles from a processor. Upon the completion of each bus cycle, the controller provides a completion indication to the processor. In the present invention, the controller withholds the completion indication for a period of time after completion of each of the selected bus cycles to control power consumption by the processor, thereby extending the time in which the processor is in the reduced power consumption state. In this way, power consumption in the processor is controlled within an instruction boundary.

REFERENCES:
patent: 4758945 (1988-07-01), Remedi
patent: 4851987 (1989-07-01), Day

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