Method of manufacturing an alignment mark with an etched back di

Details Method of manufacturing an alignment mark with an etched back di Method of manufacturing an alignment mark with an etched back di

1999-04-30

2000-08-08

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

438462, H01L 2176

Patent

active

061001589

ABSTRACT:
A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.

REFERENCES:
patent: 5786260 (1998-07-01), Jang et al.
patent: 5919714 (1999-07-01), Chen et al.
patent: 5958800 (1999-09-01), Yu et al.
patent: 5963816 (1999-10-01), Wang et al.
patent: 6015744 (2000-01-01), Tseng
patent: 6020249 (2000-02-01), Shih et al.
patent: 6043133 (2000-03-01), Jang et al.

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