Device for generating structured addresses

Details Device for generating structured addresses Device for generating structured addresses

1995-06-07

1996-12-31

Chan, Eddie P.

3954211, G06F 1210

Patent

active

055903029

ABSTRACT:
A device for generating structured addresses indicating an address position in a memory to be accessed. This device comprises first and second structured address generating devices and receives address data having a first address of i bits (i>0), a second address of n bits (n>0), and a control bit. The first structured address generation device receives the first address and a page address of m bits (m>0) corresponding to the address data and adds the high order k bits (i>k>0 and m>k>0) of the first address to the low order k bits of the page address to generate a first structured address of n bits comprising high-order m-k bits made from the high order m-k bits of the page address, intermediate order k bits made from a result of the addition, and low-order i-k bits made from the low order i-k bits of the first address. The second structured address generation device selects either the first structured address or the second address based on the control bit to generate a second structured address which is transmitted to the memory.

REFERENCES:
patent: 4959770 (1990-09-01), Kondo et al.
patent: 5109334 (1992-04-01), Kamuro
patent: 5150471 (1992-09-01), Tipon et al.
patent: 5347643 (1994-09-01), Kondo et al.

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