Method and apparatus for retarting pipeline processing

Details Method and apparatus for retarting pipeline processing Method and apparatus for retarting pipeline processing

Filed on

1995-05-24

Date issued

1996-12-31

Examiner

Treat, William M.

Other Related Categories

395800, G06F 938

Type

Patent

Status

active

Patent number

055902944

Description

ABSTRACT:
A method and apparatus for restarting an instruction processing pipeline after servicing one or more interlock processing faults. A pipeline architecture is defined in which processing interdependencies (such as instruction latencies, resource conflicts, cache accesses, virtual address translations and sign extend operations) are presumed not to be present so as to increase pipeline throughput. Interdependencies which actually occur appear as processing faults which then are serviced. At the completion of the servicing, pipeline restarting operations occur, during which the portions of the pipeline which are invalidated are preloaded. Preloading includes backing-up the invalidated stages and re-executing such stages with corrected information so as to fill the pipeline. The pipeline portions (e.g., stages) which are invalidated are determined by the type of processing fault which occurs. Upon completion of preloading, normal instruction pipeline processing resumes.

REFERENCES:
patent: 4701915 (1987-10-01), Kitamura et al.
patent: 4750112 (1988-06-01), Jones et al.
patent: 4760519 (1988-07-01), Papworth et al.
patent: 5019967 (1991-05-01), Wheeler et al.
patent: 5027270 (1991-06-01), Riordan et al.
patent: 5060148 (1991-10-01), Isobe et al.
patent: 5119483 (1992-06-01), Madden et al.
patent: 5193158 (1993-03-01), Kinney et al.
patent: 5203003 (1993-04-01), Donner
patent: 5317701 (1994-05-01), Reininger et al.
patent: 5325495 (1994-06-01), McLellan
patent: 5404552 (1995-04-01), Ikenaga
Hennessy, et. al. "The MIPS Machine" Proceeding of the IEEE Feb., 1982, pp. 2-7.
Ramamoorthy, et. al. "Pipeline Architecture" ACM Computing Surveys vol. 9, No. 1, Mar., 1977 pp. 61-101.
Hennessy "VLSI Processor Architecture" IEEE Transactions on Computers vol. C-33, No. 12, Dec., 1984 pp. 1221-1246.
"Pipelining in SISD Machine Designs" pp. 212--225.
Namjoo, et. al. "CMOS Gate Array Implementation of the SPARC Architecture" IEEE 1988 pp. 10-13.
Grohsoki "Machine Organization of the IBM RISC System/6000 Processor" IBM J. Res. Develop. vol. 34, No. 1, Jan., 1990.
Namjoo et al. CMOS Gate Array Implementation of the SPARC Architecture IEEE 1988.

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