Parallel processing data network of master and slave transputers

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

39520012, 395308, 395311, 395312, 395800, G06F 1516

Patent

active

055902847

ABSTRACT:
The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

REFERENCES:
patent: 4320452 (1982-03-01), Kempf et al.
patent: 4355354 (1982-10-01), Kempf et al.
patent: 4514807 (1985-04-01), Nogi
patent: 4591976 (1986-05-01), Webber et al.
patent: 4610013 (1986-09-01), Long et al.
patent: 4641238 (1987-02-01), Kneib
patent: 4752777 (1988-06-01), Franaszek
patent: 4800441 (1989-01-01), Sato
patent: 4811210 (1989-03-01), McAulay
patent: 4811361 (1989-03-01), Bacou et al.
patent: 4816993 (1989-05-01), Takahashi et al.
patent: 4858177 (1989-08-01), Smith
patent: 4876641 (1989-10-01), Cowley
patent: 4891751 (1990-01-01), Call et al.
patent: 4912704 (1990-03-01), Bonicioli et al.
patent: 4975913 (1990-12-01), Watanabe et al.
patent: 4989202 (1991-01-01), Soto et al.
patent: 4990985 (1991-02-01), Kamata
patent: 4992933 (1991-02-01), Taylor
patent: 5005151 (1991-04-01), Kurkowski
patent: 5014189 (1991-05-01), Tamitani
patent: 5029331 (1991-07-01), Heichler et al.
patent: 5051982 (1991-09-01), Brown et al.
patent: 5056006 (1991-10-01), Acharya et al.
patent: 5109226 (1992-04-01), Mac Lean, Jr. et al.
patent: 5111399 (1992-05-01), Armitage
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5418970 (1995-05-01), Gifford
Inmos, "The Transputer Family" (Jun. 1986) pp. 32-33.
William Stallings, "Data and Computer Communications" Fig. 1-5 (2d ed. 1988).
Martin J. Weik, "Communications Standard Dictionary" p. 1076 (2d ed. 1989).
Charles Carinalli & John Blair, `National's Advanced Graphics Chip Set for High-Performance Graphics` published in IEEE Computer Graphics and Applications, vol. 6, No. 10, Oct. 1986, New York, US pp. 40-48, XP2230.
"Scalable Coherent Interface", Jan. 1990, Authors: Knug Alnaes & Ernst H. Kristiansen--Dolphin Server Technology A.S.--Oslo, Norway; David B. Gustavson--Stanford Linear Accelerator Center--Stanford, California; David V. James--Apple Computer--Cupertino, California.
"Direct Memory Access Controller", Motorola Semiconductor Technical Data.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Parallel processing data network of master and slave transputers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel processing data network of master and slave transputers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel processing data network of master and slave transputers will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1149009

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.