Fishing – trapping – and vermin destroying
Patent
1993-03-12
1995-03-21
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 53, 148DIG111, H01L 21441, H01L 21339
Patent
active
053995252
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to integrated circuits.
In certain applications, and charge-coupled devices may be mentioned by way of example, there is a need to produce very narrow electrodes extending in length on either side of an elongate semiconductor zone. This is the case, for example, for anti-dazzle devices associated with photosensitive charge-coupled devices. Two conducting strips are often produced which are isolated from a semiconductor substrate in which charge transfers take place, these strips flanking an elongate doped semiconductor region formed in the substrate: the doped region serves as a drain for the excess charges and the conducting strips serve to create a potential barrier defining the excess level above which charges have to be drained away in order to prevent dazzling.
In the conventional technique, a polycrystalline-silicon layer is deposited in order to make up the electrodes and it is etched in order to define the semiconductor strips; then a doping impurity is implanted in the gap between two polycrystalline-silicon strips in order to make up the drain in the form of an elongate strip. But conventional photolithography techniques do not then enable the total width necessary for producing the whole unit comprising the two conducting strips separated by a doped semiconductor strip to be reduced below approximately 5 micrometers. Now, it would be preferable to reduce this width to a lower value in order to gain space in the integrated circuit.
This is why the invention provides a novel process for forming conducting strips self-aligned with doped semiconductor strips, the whole unit having a very small width.
According to the invention, a manufacturing process is provided comprising the following steps: the surface of a substrate, protected by the masking layer, this opening also extending beneath the edges of the masking layer, leaving these edges overhanging above the opening; of the overhanging edges is deposited; silicon strips remain essentially only beneath the overhanging edges.
In other words, the main point of the process according to the invention is the formation of conducting strips, the particular feature of which is that they are located beneath overhanging edges, that is to say their width is defined from the length of overhang of the edges of a masking layer which has served to define an opening in a substrate. The word substrate is taken in the wide sense, as the surface of the substrate can be a semiconductor surface or a semiconductor surface covered with an insulating layer of a certain thickness. And the opening formed in the substrate can be an opening formed in a semiconductor or an opening formed in an insulating layer.
In a particularly advantageous manner, in order to form the opening in the substrate (step c), a localised thick oxidation step (step c1) is used followed by a deoxidation step (step c2). This exploits the fact that thick oxidation steps are provided in any case for other elements of the integrated circuit, but here this step is used in unusual manner since the thick oxide formed is not preserved. The masking layer is then, more precisely, an oxidation-preventing masking layer.
An impurity will be implanted in the substrate if it is desired to define a doped semiconductor region self-aligned with the substrate; depending on the case, this impurity will be implanted before the removal of the thick oxide or after etching of the polycrystalline silicon.
In the case where the two grids adjacent to the doped semiconductor strip have to stay at identical potentials, it is possible to deposit an additional polycrystalline-silicon layer in order to fill the gap between the two grids above the doped semiconductor zone.
In general, the grids will be isolated from the semiconductor substrate by a thin insulating layer formed before deposition of the polycrystalline silicon.
The masking layer can stay or be removed at the end of the manufacturing steps indicated hereinabove.
The etching of the polycrystalline silicon at the end of
REFERENCES:
patent: 4648941 (1987-03-01), Blanchard
patent: 4692995 (1987-09-01), Blanchard
patent: 4710234 (1987-12-01), Blanchard
patent: 4724218 (1988-02-01), Blanchard et al.
patent: 4753900 (1988-06-01), Blanchard et al.
patent: 4774199 (1988-09-01), Blanchard et al.
patent: 4780394 (1988-10-01), Blanchard et al.
patent: 4873200 (1989-10-01), Kawakatsu
patent: 5219768 (1993-06-01), Okita
D. Herault et al., L'Onde Electrique, pp. 51-54, "Area Array Image Sensor for HDTV Broadcast Cameras," May/Jun. 1990.
Y. Okita et al., Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 1988, pp. 22.4.1-22.4.4, "A Novel Base-Emitter Self-Alignment Process for High Speed Bipolar LSIS".
Electronic Engineering, Jun. 1986, pp. 9, 10, 14, "New CCD Camera Variants from EEV".
Chaudhari C.
Hearn Brian E.
Plottel Roland
Thomson-CSF Semiconducteurs Specifiques
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