Multi-level semiconductor package

Details Multi-level semiconductor package Multi-level semiconductor package

1989-10-26

1991-02-19

Jackson, Jr., Jerome

357 72, 357 65, H01L 2302

Patent

active

049948970

ABSTRACT:
A single-in-line semiconductor package uses a multi-level heatsink having patterned conductors surrounding the semiconductor device. The patterned conductors are electrically isolated from the heatsink. Short bond wires are used to connect the semiconductor device to the patterned conductors. This arrangement eliminates the need for bonding shelves when bonding the leads and also increases the resistance of the bond wires from being swept away during encapsulation.

REFERENCES:
patent: 4032706 (1977-06-01), Paletto
patent: 4132856 (1979-01-01), Hutchison et al.
patent: 4807018 (1989-02-01), Cellai

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