TTL-to-CML translator circuit

Details TTL-to-CML translator circuit TTL-to-CML translator circuit

1990-04-16

1991-02-19

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307455, 3072966, H03K 17092, H03K 1716

Patent

active

049946919

ABSTRACT:
A TTL-to-CML translator circuit includes a TTL input stage (20), a translation chain (22), a first CML differential pair (24), a level shifter (26), and a second CML differential pair (28). The first CML differential pair (24) is coupled between a TTL ground potential (GTTL) and a negative supply potential (VEE). The second CML differential pair (28) is connected between a CML ground potential (GCML) and the negative supply potential. The level shifter (26) serves to electrically isolate the TTL ground potential and the CML ground potential, thereby producing relatively noise free CML-compatible output signals.

REFERENCES:
patent: 4656370 (1987-04-01), Kanuma
patent: 4698527 (1987-10-01), Matsumoto
patent: 4806800 (1989-02-01), Khan
patent: 4857776 (1989-09-01), Khan
patent: 4883978 (1989-11-01), Ohshima et al.

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