Powered testing of mixed conventional/boundary-scan logic

Details Powered testing of mixed conventional/boundary-scan logic Powered testing of mixed conventional/boundary-scan logic

1992-01-03

1993-11-09

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

371 223, G01R 3128

Patent

active

052606490

ABSTRACT:
The (X,Y) positions of the nodes in a circuit containing boundary scan components and non-boundary scan components are stored in a computer. The computer selects a set of non-boundary scan nodes within a radius R of a selected boundary-scan node, R being the length of solder bridges in the circuit. A logic 0 voltage is applied to the set and a boundary-scan test is performed. If the boundary-scan test fails, a fault is declared in the circuit between the set and the selected boundary-scan node. A logic 1 voltage is applied to one of the nodes in the set, and the test repeated. If the test returns different results, the fault is declared between that one node and the selected boundary-scan node. A time limit is established for each non-boundary scan node corresponding to the length of time a short in that node can be tolerated. The boundary-scan nodes in the circuit are tested in the order of ascending time limits in its associated set. Power is cut off to the circuit if the time limit of a node not yet tested, or tested and failed, is exceeded.

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Hewlett Packard Boundary-Scan Tutorial and BSDL Reference Guide, Dec. 1990 "Interconnect Testing of Boards with Partial Boundary Scan" by Gordon D. Robinson & John G. Deshayes of GenRad, Inc. 1990 International Test Conference.

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