Logic circuit uising transistor having negative differential con

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307322, 307471, H03K 19013, H03K 4787

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active

052606090

ABSTRACT:
A logic circuit first, second and third input terminals, an output terminal, a load resistance element, and a transistor having a negative differential conductance. The collector is connected to the output terminal and coupled to a first power source via the load resistance element. The emitter is connected to a second power source. First, second and third resistors are connected between the base of the transistor and the first, second and third input terminals, respectively. A fourth resistor is connected between the base and emitter of the transistor. The resistance values of the first, second, third and fourth resistors are selected so that the transistor has first and second operating points respectively obtained when all the first, second and third input terminals are at a low level and when two of the first, second and third input terminals are at a high level, and has third and fourth operating points respectively obtained when one of the first, second and third input terminals is at the high level and when all the first, second and third input terminals are at the high level. A collector current obtained at the first and second operating points is less than that obtained at the third and fourth operating points.

REFERENCES:
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patent: 4868415 (1989-09-01), Imamura et al.
M. Suzuki et al., "Gate Arrays", 1988 IEEE International Solid-State Circuits Conference, ISSCC 88, Wednesday, Feb. 17, 1988, pp. 70-71.
N. Yokoyama et al., "A New Functional, Resonant-Tunnelling Hot Electron Transistor (RHET)", Japanese Journal of Applied Physics, vol. 24, No. 11, Nov. 1985, pp. L853-L854.
T. Futatsugi et al., "A Resonant-Tunnelling Bipolar Transistor (RBT)-A New Functional Device with High Current Gain", Japanese Journal of Applied physics, vol. 26, No. 2, Feb. 1987, pp. L131-L133.
M. Shur, et al., "New Negative Resistance Regime of Heterostructure Insulated Gate Transistor (HIGFET) Operation", IEEE Electron Device Letters, vol. EDL-7, No. 2, Feb. 1986, pp. 78-80.

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