Fishing – trapping – and vermin destroying
Patent
1989-08-28
1991-02-19
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 27, 437 28, 437 29, 437 30, 437 41, 357 233, 156643, 156646, H01L 21312, H01L 21265
Patent
active
049944045
ABSTRACT:
A process is disclosed for the formation of an LDD structure in an MOS transistor having a reduced mask count and providing high integrity source/drain junctions. In accordance with one embodiment of the invention an MOS transistor is formed having a gate dielectric overlying an active region of the substrate. A transistor gate is formed in a central portion of the active region and an oxidation layer is formed over the active region and the transistor gate. A lightly-doped source/drain region is formed which is self aligned to the transistor gate. A conformal layer of an oxygen reactive material is formed overlying the transistor gate and the active region. The oxygen reactive material is anisotropically etched in a oxygen plasma reactive ion etch to form a sidewall spacer on the edge the transistor gate. The oxygen reactive ion etch does not penetrate the oxidation layer overlying the active region. A heavily-doped source/drain region is formed which is self aligned to the edge of the sidewall spacer. The sidewall spacer is then removed completing the LDD structure.
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Cullen Mark J.
Kosa Yasunobu
Sheng David Y.
Urquhart Andrew J.
Chaudhuri Olik
Dockrey Jasper W.
Motorola Inc.
Wilczewski M.
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