Memory access control system for use with a relatively small siz

Details Memory access control system for use with a relatively small siz Memory access control system for use with a relatively small siz

1991-04-22

1994-01-18

Rudolph, Rebecca L.

Boots, shoes, and leggings

364DIG1, 364240, 3642402, 364239, G06F 100

Patent

active

052805891

ABSTRACT:
A memory access control system is disclosed. In this system, a CPU, a low speed memory, a high speed memory and direct memory access controller (DMAC) are connected to a system bus. A high speed memory is connected through a local bus to the CPU. A control circuit is connected to the local bus, the system bus and the high speed memory. A bidirectional buffer is connected to the local and system buses. When the CPU accesses the high speed memory, the control circuit addresses the high speed memory and disables the buffer. As a result, data can directly be transferred between the CPU and the high speed memory. When the CPU accesses the low speed memory, the control circuit drives the system bus according to a protocol of the system bus, thereby to address the low speed memory and enables the buffer. As a result, data can be transferred between the CPU and the low speed memory, via a route of the local bus, the buffer and the system bus. When the DMAC accesses the high speed memory, the control circuit addresses the high speed memory and enables the buffer according to the system bus protocol. As a result, data can be transferred between the DMAC and the high speed memory, through a route of the local bus, the buffer, and the system bus. When the DMAC accesses the low speed memory, the control circuit disables the high speed memory and the buffer.

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