Process for fabricating a high-voltage MOSFET

Details Process for fabricating a high-voltage MOSFET Process for fabricating a high-voltage MOSFET

1995-07-28

1996-12-31

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 44, H01L 21265

Patent

active

055894119

ABSTRACT:
A process for fabricating high-voltage MOSFET devices on a semiconductor substrate is disclosed. The substrate has heavily-doped impurities of a first conductivity type, and constitutes the drain region for the MOSFET. The process of fabrication comprises the steps of subsequently forming on the substrate a first doped layer, a second doped layer, a third doped layer and a shielding layer. All of these doped layers are of the first conductivity type. The second doped layer has an impurity concentration and a thickness smaller and larger than the impurity concentration and thickness respectively of the first doped layer, and larger and smaller than the impurity concentration and thickness respectively of the third doped layer. The impurity concentration of the first doped layer is smaller than the impurity concentration of the substrate. An opening in the shielding layer is formed, and then the source region of the MOSFET is formed in the area exposed by the opening. Afterwards, thermal oxidation is performed to form a field oxide layer over the surface of the source region. Next, an etching process is performed to remove the third doped layer, thereby revealing the surface of said second doped layer to form a source protruding body. Sidewalls of the source protruding body is then covered by an insulating layer. Finally, the field oxide layer and the insulating layer are then utilized as masking for implanting impurities of a second conductivity type into the second doped layer, thereby forming the gate region for the MOSFET.

REFERENCES:
patent: 4543706 (1985-10-01), Bencuya et al.
patent: 5385852 (1995-01-01), Oppermann et al.

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