Reed-Solomon code system employing k-bit serial techniques for e

Details Reed-Solomon code system employing k-bit serial techniques for e Reed-Solomon code system employing k-bit serial techniques for e

1990-11-08

1994-01-18

Baker, Stephen M.

Excavating

371 391, G06F 1110

Patent

active

052804887

ABSTRACT:
Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

REFERENCES:
patent: 4099160 (1978-07-01), Flagg
patent: 4142174 (1979-02-01), Chen et al.
patent: 4410989 (1983-10-01), Berlekamp
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4584686 (1986-04-01), Fritze
patent: 4730321 (1988-03-01), Machado
patent: 4769818 (1988-09-01), Mortimer
patent: 4777635 (1988-10-01), Glover
patent: 4782490 (1988-11-01), Tenengolts
patent: 4833678 (1989-05-01), Cohen
patent: 4839896 (1989-06-01), Glover et al.
patent: 4843607 (1989-06-01), Tong
patent: 4975915 (1990-12-01), Sako et al.
Berlekamp, E., "Bit-Serial Reed-Solomon Encoders", IEEE Trans. on Information Theory, vol. 1T-28, No. 6, Nov. 1982, pp. 869-874.
Maki, G. et al., "A VLSI Reed Solomon Encoder: An Engineering Approach", IEEE Custom Integrated Circuits Conf., 1986, pp. 177-181.
Beth, T. et al., "Architectures for Exponentiation in GF (2.sup.n)", Advances in Cryptology-CRYPTO '86 Proceedings , Springer-Verlag, pp. 302-310.
Glover, N. et al., Practical Error Correction Design for Engineers, 1988, Data Systems Technology Corp., pp. 181-184, 186, 194-196.
Peterson, W. et al., Error-Correcting Codes, 1972, MIT Press, pp. 277, 472-476.
Clark and Cain, Error Correction Coding For Digital Communications, "Algebraic Techniques For Multiple Error Correction" Chapter 5, pp. 181-225.
Practical Error Correction Design For Engineers, Second Edition, Neal Glover and Trent Dudley, pp. 11-13, 32-34, 89-90, 112-113, 181, 242, 270, 285, 296, 298, 350.

Affiliated with

Also associated with

Rating

Reed-Solomon code system employing k-bit serial techniques for e does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reed-Solomon code system employing k-bit serial techniques for e, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reed-Solomon code system employing k-bit serial techniques for e will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1141211