Data processing system having a central main memory and a plural

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G06F 300, G06F 1300

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active

045637385

ABSTRACT:
For the purpose of connecting a plurality of independent processor units to a single port of a main memory, the processor units are connected in series over individual interface controls, whereby the interfaces are expanded in comparison to the port interface without the interface conditions for the port being changed. The interface controls operate in reciprocal dependency on one another so that the memory access request arising within the processor unit chain becomes effective in individual succession by way of a reciprocal inhibiting without address control, whereby variable connector controls in the interface lines determine the transmission path of both directions between the main memory and the respectively active processor depending upon status signals which, among other things, are influenced by interface signals. Termination of a write operation and clear down of a completed connection occurs by way of an internal interface line of the chain circuit. Given a read operation, the clear down of the connection path to the memory for the request already occurs with the beginning of the read data transmission given completion of the return connection path. For an additional lock mode, two additional internal interface lines are provided in conjunction with a monitoring and inhibit control in each interface control.

REFERENCES:
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patent: 4257095 (1981-03-01), Nadir
Computer Dictionary and Handbook Sippl and Sippl, Howard W. Sams & Co. Inc., 1972, pp. 261 and 487.
Leipold et al., "Organisation des Nachrichtenverkehrs zwischen Zentral-einheiten und peripheren Einheiten in Datenverarbeitungssystemen", Elektronishche Rechenanlagen, vol. 11, No. 3, 1969, pp. 151-161.
Both, R., "Einfluss der Prozessor-Speicher-Verbindungssystems auf die Leistung von Multiprozessor-Anlagen", Elektronishce Rechenanlagen, vol. 23, No. 3, 1981, pp. 107-115.

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