Capacitive coupled summing circuit with signed output

Details Capacitive coupled summing circuit with signed output Capacitive coupled summing circuit with signed output

1994-02-15

1995-11-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

G06G 742

Patent

active

054691028

ABSTRACT:
A summing circuit for executing summing of analog data with sign. The summing circuit includes two serially connected inverters INV1 and INV2, each having a feed back line, and selectively inputs data D1 to D8 to one of the first or the second stages, corresponding to positive
egative sign signals S1 to S8.

REFERENCES:
patent: 3921080 (1975-11-01), Hardy
patent: 3970774 (1976-07-01), Bazin et al.
patent: 4835482 (1989-05-01), Tamakoshi et al.
patent: 4903226 (1990-02-01), Tsividis
Patent Abstracts of Japan, vol. 4, No. 67 (E-100) 20 May 1980 & JP-A-55 034 593; English abstract.
Patent Abstracts of Japan, vol. 13, No. 201 (E-757) 12 May 1989 & JP-A-01 020 788; English abstract.
Derwent Abstract--Soviet Inventions Illustrated, Section EQ, Week 8548, 23 May 1985, AN 85-301827 & SU-A-1 157 677 (May 1985).

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