Look-ahead asynchronous register set/reset in programmable logic

Details Look-ahead asynchronous register set/reset in programmable logic Look-ahead asynchronous register set/reset in programmable logic

1992-05-15

1994-01-18

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072722, 307480, H03K 19173

Patent

active

052802035

ABSTRACT:
A programmable logic device in which macrocell register reset time, T.sub.clear, and set time, T.sub.set, are comparable in speed to the combinatorial propagation delay time, T.sub.pd. In setting or resetting the macrocell register, the Set (Reset) signal is applied simultaneously to a clocked master latch in the macrocell register and to an output node. During the Set (Reset) period the slave latch of the macrocell register is disconnected from the output node.

REFERENCES:
patent: 4777623 (1988-10-01), Shimazu et al.
patent: 4849653 (1989-07-01), Imai et al.
patent: 4974241 (1990-11-01), McClure et al.
patent: 5087835 (1992-02-01), Hattangadi

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