Method of making trench EEPROM structure on SOI with dual channe

Details Method of making trench EEPROM structure on SOI with dual channe Method of making trench EEPROM structure on SOI with dual channe

1994-04-29

1995-05-02

Thomas, Tom

Fishing, trapping, and vermin destroying

437 21, 437 52, 437203, H01L 218247

Patent

active

054119057

ABSTRACT:
A structure and fabrication method for an EEPROM cell having dual channel regions and the floating and control gate folded inside a trench. The cell is built on a SOI film substrate and the bottom part of the floating gate is butted to oxide, which provides high coupling factor. Inside the trench, the floating gates are butted to the conducting channels on two sidewalls, respectively. On the other two sidewalls, the floating gate are butted to the source and drain elements (bit line). These two sidewalls are used as the injection regions of FN tunnelling between source/drain and the floating gate or the isolation regions between bit lines. Since FN tunnelling (program and erase) occurs at the two trench sidewalls against the source and drain, program/erase speed is increased by increasing trench depth while maintaining cell size constant.

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