Method of placing source contacts for efficient ESD/EOS protecti

Details Method of placing source contacts for efficient ESD/EOS protecti Method of placing source contacts for efficient ESD/EOS protecti

1994-12-15

1995-11-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 51, H01L 218234

Patent

active

054686679

ABSTRACT:
An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).

REFERENCES:
patent: 4692781 (1987-09-01), Rountree et al.
patent: 4893168 (1990-01-01), Takahashi et al.
patent: 4952994 (1990-08-01), Lin
patent: 5166089 (1992-11-01), Chen et al.
patent: 5229635 (1993-07-01), Bessolo et al.

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