Data transfer control system

Details Data transfer control system Data transfer control system

1983-06-20

1987-02-24

Thomas, James D.

Boots, shoes, and leggings

G06F 1206

Patent

active

046462309

ABSTRACT:
A data transfer control system which is provided between a main memory for storing programs, data and channel control blocks (CCB's) and I/O processors for controlling channels, for converting an address from the I/O processors to an address specifying the main memory, first address memory which is addressed by combination data of a first identification number identifying the I/O processors and a second identification number identifying the channel and stores a CCB start address of the main memory; second address memory which is addressed by the combination data and stores a start address in a data transfer section included in the channel control block; and a data controller in which, when the first and second identification numbers, a flag, and a relative address are received from the channels through the I/O processors, one of the first and second address memories is selected in accordance with the flag value, the data controller generating an address by adding the address read out from the selected memory and the relative address and then sending the added address to the main memory.

REFERENCES:
patent: 4092715 (1978-05-01), Scriver
patent: 4133030 (1979-01-01), Huettner et al.
patent: 4155119 (1979-05-01), DeWard et al.
patent: 4156932 (1979-05-01), Robinson et al.

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