Instruction set modifier register

Details Instruction set modifier register Instruction set modifier register

1978-03-13

1980-11-25

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 930

Patent

active

042362040

ABSTRACT:
An instruction set modifier register, comprising one or more bistable latches which are loadable under program control, is provided for use in a processor in conjunction with an instruction register. An instruction decoding circuit and an instruction execution control logic circuit, responsive to both the instruction register and the instruction set modifier register, generate a first set of control signal combinations corresponding to a first instruction set when the instruction set modifier register is in a first state and generate a second set of control signal combinations corresponding to a second instruction set when the instruction set modifier register is in a second state. The processor is thus able to execute more than one set of instructions, utilizing the same instruction decoding circuitry and instruction execution control logic circuitry.

REFERENCES:
patent: 3764988 (1973-10-01), Onishi
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 3997895 (1976-12-01), Cassonnet et al.

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