Gate controlled negative resistance semiconductor device

Details Gate controlled negative resistance semiconductor device Gate controlled negative resistance semiconductor device

1979-05-23

1980-11-25

Wojciechowicz, Edward J.

357 21, 357 23, 357 55, 357 89, 357 90, 357 91, H01L 2966

Patent

active

042361702

ABSTRACT:
A negative resistance semiconductor device comprises at least one negative resistance semiconductor element. The negative resistance semiconductor element includes a first region of N type and a second region of P type for forming a PN junction. A conductive electrode is provided on an insulating layer on the first region and is electrically coupled with the second region. First and second terminals are connected to the first and second regions, respectively. A region doped with an impurity of N type is provided on the surface of a subregion of the first region between the PN junction and the remaining subregion of the first region, and a region doped with an impurity of the P type is formed on the subregion. A negative resistance characteristics is obtained when a reverse bias voltage of a predetermined range is applied between the first and second terminals.

REFERENCES:
patent: 3654531 (1972-04-01), Krambeck et al.
Solid State Elec.--vol. 9, pp. 783-806, A. S. Grove et al. 1966.
IEEE Jour. Solid State Circuits--vol. SC-11, No. 1, pp. 58-63, Tasch et al., Feb. 1976.

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