Semiconductor integrated circuit isolated through dielectric mat

Details Semiconductor integrated circuit isolated through dielectric mat Semiconductor integrated circuit isolated through dielectric mat

1976-10-26

1978-12-26

Larkins, William D.

357 23, 357 41, 357 59, 357 67, 29571, H01L 2712, H01L 2978, H01L 2702, H01L 2904

Patent

active

041319095

ABSTRACT:
A semiconductor integrated circuit includes first and second island regions, surrounded by a bottomed dishlike dielectric layer formed on one side of a support body. A MOS transistor element is formed in the first island region, whose gate region is located at the bottom side of the island region. The gate electrode is connected to a bottom portion of the second island region, which is used as a gate electrode contact region, in the support body using a interconnection lead. There is a method for manufacturing the above device.

REFERENCES:
patent: 3191061 (1965-06-01), Weimer
patent: 3381182 (1968-04-01), Thornton
patent: 3407479 (1968-10-01), Fordemwalt et al.
patent: 3475664 (1969-10-01), DeVries
patent: 3514676 (1970-05-01), Fa
patent: 3602981 (1971-09-01), Kooi
patent: 3865649 (1975-02-01), Beasom
patent: 3874918 (1975-04-01), Nechtow et al.
patent: 3944447 (1976-03-01), Magdo et al.

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit isolated through dielectric mat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit isolated through dielectric mat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit isolated through dielectric mat will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1131530