High speed bus with virtual memory data transfer and rerun cycle

Details High speed bus with virtual memory data transfer and rerun cycle High speed bus with virtual memory data transfer and rerun cycle

1989-06-28

1990-06-26

Zache, Raulfe B.

Boots, shoes, and leggings

364240, 3642401, 3642403, 3642563, G06F 1300

Patent

active

049377345

ABSTRACT:
A high speed data transfer bus with virtual memory capability. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. This minimizes the number of lines required to implement the bus and minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Control signals are employed that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

REFERENCES:
patent: 4378591 (1983-03-01), Lemay
patent: 4803621 (1989-02-01), Kelly

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